A method for optimizing test bus assignment and sizing for system-on-a-chip
Test access mechanism (TAM) is an important element of test access architectures for embedded cores and is responsible for on-chip test patterns transport from the source to the core under test to the sink. Efficient TAM design is of critical importance in SOC system integration since it directly im...
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| Format: | conferenceObject |
| Published: |
2017
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| Online Access: | http://hdl.handle.net/10725/5456 http://dx.doi.org/10.1109/CCECE.2007.30 http://libraries.lau.edu.lb/research/laur/terms-of-use/articles.php http://ieeexplore.ieee.org/abstract/document/4232689/ |
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