An effective solution to thermal-aware test scheduling on network-on-chip using multiple clock rates
As more cores are being packed on a single chip, bus-based communication is suffering from bandwidth and scalability issues. As a result, the new approach is to use a network-on-chip (NoC) as the main communication platform on a SoC. NoC provides the flexibility and scalability much needed in the er...
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| Format: | conferenceObject |
| Published: |
2017
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| Online Access: | http://hdl.handle.net/10725/5447 http://dx.doi.org/10.1109/MWSCAS.2012.6292074 http://libraries.lau.edu.lb/research/laur/terms-of-use/articles.php http://ieeexplore.ieee.org/abstract/document/6292074/ |
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| Summary: | As more cores are being packed on a single chip, bus-based communication is suffering from bandwidth and scalability issues. As a result, the new approach is to use a network-on-chip (NoC) as the main communication platform on a SoC. NoC provides the flexibility and scalability much needed in the era of multi-cores. NoC-based systems also provide the capability of multiple clocking that is widely used in many SoC nowadays. In this paper, a simulated annealing algorithm for thermal and power-aware test scheduling of cores in a NoC-based SoC using multiple clock rates is presented. Results on different benchmarks show the effectiveness of our technique. |
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