Test bus assignment, sizing, and partitioning for system-on-chip
The test access mechanism (TAM) is an important element of test architectures for embedded cores and is responsible for on-chip test pattern transport from the source to the core under test to the sink. Efficient TAM design is of critical importance in system-on-chip integration since it directly im...
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| Main Author: | Harmanani, Haidar M. (author) |
|---|---|
| Other Authors: | Sawan, Rachel (author) |
| Format: | article |
| Published: |
2007
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| Online Access: | http://hdl.handle.net/10725/3528 http://dx.doi.org/10.1109/CJECE.2007.4413128 http://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=4413128 |
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