On Power-Constrained System-on-chip Test Scheduling Using Precedence Relationships
This paper presents an efficient method to determine minimum SOC test schedules based on simulated annealing. The problem is solved using a partitioned testing scheme with run to completion that minimizes the number of idle test slots. The method handles SOC test scheduling with and without power co...
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| Format: | conferenceObject |
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2017
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| Online Access: | http://hdl.handle.net/10725/5459 http://dx.doi.org/10.1109/NEWCAS.2006.250936 http://libraries.lau.edu.lb/research/laur/terms-of-use/articles.php http://ieeexplore.ieee.org/abstract/document/4016967/ |
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| _version_ | 1864513477061640192 |
|---|---|
| author | Harmanani, Haidar M. |
| author2 | Salamy, Hassan A. |
| author2_role | author |
| author_facet | Harmanani, Haidar M. Salamy, Hassan A. |
| author_role | author |
| dc.creator.none.fl_str_mv | Harmanani, Haidar M. Salamy, Hassan A. |
| dc.date.none.fl_str_mv | 2017-03-29T12:04:07Z 2017-03-29T12:04:07Z 2017-03-29 |
| dc.identifier.none.fl_str_mv | http://hdl.handle.net/10725/5459 http://dx.doi.org/10.1109/NEWCAS.2006.250936 Harmanani, H. M., & Salamy, H. A. (2006, June). On Power-Constrained System-On-Chip Test Scheduling Using Precedence Relationships. In Circuits and Systems, 2006 IEEE North-East Workshop on (pp. 125-128). IEEE. http://libraries.lau.edu.lb/research/laur/terms-of-use/articles.php http://ieeexplore.ieee.org/abstract/document/4016967/ |
| dc.language.none.fl_str_mv | en |
| dc.publisher.none.fl_str_mv | IEEE |
| dc.rights.*.fl_str_mv | info:eu-repo/semantics/openAccess |
| dc.title.none.fl_str_mv | On Power-Constrained System-on-chip Test Scheduling Using Precedence Relationships |
| dc.type.none.fl_str_mv | Conference Paper / Proceeding info:eu-repo/semantics/publishedVersion info:eu-repo/semantics/conferenceObject |
| description | This paper presents an efficient method to determine minimum SOC test schedules based on simulated annealing. The problem is solved using a partitioned testing scheme with run to completion that minimizes the number of idle test slots. The method handles SOC test scheduling with and without power constraints in addition to precedence constraints that preserve desirable orderings among tests. The authors present experimental results for various SOC examples that demonstrate the effectiveness of the method. The method achieved optimal test schedules in all attempted cases in a short CPU time |
| eu_rights_str_mv | openAccess |
| format | conferenceObject |
| id | LAURepo_75dae36ee2ff2909dca08d566ad13c84 |
| identifier_str_mv | Harmanani, H. M., & Salamy, H. A. (2006, June). On Power-Constrained System-On-Chip Test Scheduling Using Precedence Relationships. In Circuits and Systems, 2006 IEEE North-East Workshop on (pp. 125-128). IEEE. |
| language_invalid_str_mv | en |
| network_acronym_str | LAURepo |
| network_name_str | Lebanese American University repository |
| oai_identifier_str | oai:laur.lau.edu.lb:10725/5459 |
| publishDate | 2017 |
| publisher.none.fl_str_mv | IEEE |
| repository.mail.fl_str_mv | |
| repository.name.fl_str_mv | |
| repository_id_str | |
| spelling | On Power-Constrained System-on-chip Test Scheduling Using Precedence RelationshipsHarmanani, Haidar M.Salamy, Hassan A.This paper presents an efficient method to determine minimum SOC test schedules based on simulated annealing. The problem is solved using a partitioned testing scheme with run to completion that minimizes the number of idle test slots. The method handles SOC test scheduling with and without power constraints in addition to precedence constraints that preserve desirable orderings among tests. The authors present experimental results for various SOC examples that demonstrate the effectiveness of the method. The method achieved optimal test schedules in all attempted cases in a short CPU timeN/AIEEE2017-03-29T12:04:07Z2017-03-29T12:04:07Z2017-03-29Conference Paper / Proceedinginfo:eu-repo/semantics/publishedVersioninfo:eu-repo/semantics/conferenceObjecthttp://hdl.handle.net/10725/5459http://dx.doi.org/10.1109/NEWCAS.2006.250936Harmanani, H. M., & Salamy, H. A. (2006, June). On Power-Constrained System-On-Chip Test Scheduling Using Precedence Relationships. In Circuits and Systems, 2006 IEEE North-East Workshop on (pp. 125-128). IEEE.http://libraries.lau.edu.lb/research/laur/terms-of-use/articles.phphttp://ieeexplore.ieee.org/abstract/document/4016967/eninfo:eu-repo/semantics/openAccessoai:laur.lau.edu.lb:10725/54592021-03-19T10:00:56Z |
| spellingShingle | On Power-Constrained System-on-chip Test Scheduling Using Precedence Relationships Harmanani, Haidar M. |
| status_str | publishedVersion |
| title | On Power-Constrained System-on-chip Test Scheduling Using Precedence Relationships |
| title_full | On Power-Constrained System-on-chip Test Scheduling Using Precedence Relationships |
| title_fullStr | On Power-Constrained System-on-chip Test Scheduling Using Precedence Relationships |
| title_full_unstemmed | On Power-Constrained System-on-chip Test Scheduling Using Precedence Relationships |
| title_short | On Power-Constrained System-on-chip Test Scheduling Using Precedence Relationships |
| title_sort | On Power-Constrained System-on-chip Test Scheduling Using Precedence Relationships |
| url | http://hdl.handle.net/10725/5459 http://dx.doi.org/10.1109/NEWCAS.2006.250936 http://libraries.lau.edu.lb/research/laur/terms-of-use/articles.php http://ieeexplore.ieee.org/abstract/document/4016967/ |