On Power-Constrained System-on-chip Test Scheduling Using Precedence Relationships
This paper presents an efficient method to determine minimum SOC test schedules based on simulated annealing. The problem is solved using a partitioned testing scheme with run to completion that minimizes the number of idle test slots. The method handles SOC test scheduling with and without power co...
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| Main Author: | Harmanani, Haidar M. (author) |
|---|---|
| Other Authors: | Salamy, Hassan A. (author) |
| Format: | conferenceObject |
| Published: |
2017
|
| Online Access: | http://hdl.handle.net/10725/5459 http://dx.doi.org/10.1109/NEWCAS.2006.250936 http://libraries.lau.edu.lb/research/laur/terms-of-use/articles.php http://ieeexplore.ieee.org/abstract/document/4016967/ |
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