Harmanani, H. M., & Salamy, H. A. (2006). A Simulated Annealing Algorithm for System-on-Chip Test Scheduling with, Power and Precedence Constraints.
Chicago Style (17th ed.) CitationHarmanani, Haidar M., and Hassan A. Salamy. A Simulated Annealing Algorithm for System-on-Chip Test Scheduling with, Power and Precedence Constraints. 2006.
MLA (9th ed.) CitationHarmanani, Haidar M., and Hassan A. Salamy. A Simulated Annealing Algorithm for System-on-Chip Test Scheduling with, Power and Precedence Constraints. 2006.
Warning: These citations may not always be 100% accurate.