Register binding for FPGAs with embedded memory
The trend in new state-of-the-art FPGAs is to have large amounts of on-chip embedded memory blocks. These memory blocks are used to hold the input/output data for various applications. Existing register binding techniques in high-level synthesis aim at minimizing the storage requirements of circuits...
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| Format: | conferenceObject |
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2017
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| Online Access: | http://hdl.handle.net/10725/5807 http://dx.doi.org/10.1109/FCCM.2004.49 http://libraries.lau.edu.lb/research/laur/terms-of-use/articles.php http://ieeexplore.ieee.org/abstract/document/1364627/ |
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| Summary: | The trend in new state-of-the-art FPGAs is to have large amounts of on-chip embedded memory blocks. These memory blocks are used to hold the input/output data for various applications. Existing register binding techniques in high-level synthesis aim at minimizing the storage requirements of circuits by sharing variables among registers and thus minimizing the required number of registers for a specific design. In this paper, a new technique is proposed that makes use of the existing embedded memory blocks and maps variables to these blocks. The proposed memory binding approach gives considerable performance increase over the existing register binding techniques. The memory binding technique resulted in up to 57% savings in the total chip area (number of logic cells/elements occupied on the FPGA) over the old register binding techniques for a small resource bag and up to 6% savings for a large resource bag. |
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