An Ant Colony Optimization approach for test pattern generation
Test pattern generation is a challenging problem that has an exponential complexity that is aggravated with the continuos increase in circuits size. This paper deals with automatic test pattern generation (ATPG) for combinational circuits, and proposes a new approach based on Ant Colony Optimization...
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| المؤلف الرئيسي: | |
|---|---|
| التنسيق: | conferenceObject |
| منشور في: |
2017
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| الوصول للمادة أونلاين: | http://hdl.handle.net/10725/5455 http://dx.doi.org/10.1109/CCECE.2008.4564771 http://libraries.lau.edu.lb/research/laur/terms-of-use/articles.php http://ieeexplore.ieee.org/abstract/document/4564771/ |
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| _version_ | 1864513477056397312 |
|---|---|
| author | Harmanani, Haidar M. |
| author_facet | Harmanani, Haidar M. |
| author_role | author |
| dc.creator.none.fl_str_mv | Harmanani, Haidar M. |
| dc.date.none.fl_str_mv | 2017-03-29T10:18:27Z 2017-03-29T10:18:27Z 2017-03-29 |
| dc.identifier.none.fl_str_mv | 978-1-4244-1642-4 http://hdl.handle.net/10725/5455 http://dx.doi.org/10.1109/CCECE.2008.4564771 Farah, R., & Harmanani, H. M. (2008, May). An Ant Colony Optimization approach for test pattern generation. In Electrical and Computer Engineering, 2008. CCECE 2008. Canadian Conference on (pp. 001397-001402). IEEE. http://libraries.lau.edu.lb/research/laur/terms-of-use/articles.php http://ieeexplore.ieee.org/abstract/document/4564771/ |
| dc.language.none.fl_str_mv | en |
| dc.publisher.none.fl_str_mv | IEEE |
| dc.rights.*.fl_str_mv | info:eu-repo/semantics/openAccess |
| dc.title.none.fl_str_mv | An Ant Colony Optimization approach for test pattern generation |
| dc.type.none.fl_str_mv | Conference Paper / Proceeding info:eu-repo/semantics/publishedVersion info:eu-repo/semantics/conferenceObject |
| description | Test pattern generation is a challenging problem that has an exponential complexity that is aggravated with the continuos increase in circuits size. This paper deals with automatic test pattern generation (ATPG) for combinational circuits, and proposes a new approach based on Ant Colony Optimization (ACO). The paper studies the opportunities offered by ACO in comparison with other simulated-based ATPGs. The method is implemented and is shown to efficiently generate a set of test vectors that achieve a high fault coverage in a short time. Several benchmark circuits are attempted, and favorable results comparisons are reported |
| eu_rights_str_mv | openAccess |
| format | conferenceObject |
| id | LAURepo_c477d9252ae33011dfb5d008d99dd402 |
| identifier_str_mv | 978-1-4244-1642-4 Farah, R., & Harmanani, H. M. (2008, May). An Ant Colony Optimization approach for test pattern generation. In Electrical and Computer Engineering, 2008. CCECE 2008. Canadian Conference on (pp. 001397-001402). IEEE. |
| language_invalid_str_mv | en |
| network_acronym_str | LAURepo |
| network_name_str | Lebanese American University repository |
| oai_identifier_str | oai:laur.lau.edu.lb:10725/5455 |
| publishDate | 2017 |
| publisher.none.fl_str_mv | IEEE |
| repository.mail.fl_str_mv | |
| repository.name.fl_str_mv | |
| repository_id_str | |
| spelling | An Ant Colony Optimization approach for test pattern generationHarmanani, Haidar M.Test pattern generation is a challenging problem that has an exponential complexity that is aggravated with the continuos increase in circuits size. This paper deals with automatic test pattern generation (ATPG) for combinational circuits, and proposes a new approach based on Ant Colony Optimization (ACO). The paper studies the opportunities offered by ACO in comparison with other simulated-based ATPGs. The method is implemented and is shown to efficiently generate a set of test vectors that achieve a high fault coverage in a short time. Several benchmark circuits are attempted, and favorable results comparisons are reportedN/AIEEE2017-03-29T10:18:27Z2017-03-29T10:18:27Z2017-03-29Conference Paper / Proceedinginfo:eu-repo/semantics/publishedVersioninfo:eu-repo/semantics/conferenceObject978-1-4244-1642-4http://hdl.handle.net/10725/5455http://dx.doi.org/10.1109/CCECE.2008.4564771Farah, R., & Harmanani, H. M. (2008, May). An Ant Colony Optimization approach for test pattern generation. In Electrical and Computer Engineering, 2008. CCECE 2008. Canadian Conference on (pp. 001397-001402). IEEE.http://libraries.lau.edu.lb/research/laur/terms-of-use/articles.phphttp://ieeexplore.ieee.org/abstract/document/4564771/eninfo:eu-repo/semantics/openAccessoai:laur.lau.edu.lb:10725/54552021-03-19T10:00:56Z |
| spellingShingle | An Ant Colony Optimization approach for test pattern generation Harmanani, Haidar M. |
| status_str | publishedVersion |
| title | An Ant Colony Optimization approach for test pattern generation |
| title_full | An Ant Colony Optimization approach for test pattern generation |
| title_fullStr | An Ant Colony Optimization approach for test pattern generation |
| title_full_unstemmed | An Ant Colony Optimization approach for test pattern generation |
| title_short | An Ant Colony Optimization approach for test pattern generation |
| title_sort | An Ant Colony Optimization approach for test pattern generation |
| url | http://hdl.handle.net/10725/5455 http://dx.doi.org/10.1109/CCECE.2008.4564771 http://libraries.lau.edu.lb/research/laur/terms-of-use/articles.php http://ieeexplore.ieee.org/abstract/document/4564771/ |