Thermal-aware test scheduling using network-on-chip under multiple clock rates
The increasing trend in the number of cores on a single chip has led to scalability and bandwidth issues in bus-based communication. Network-on-chip (NoC) techniques have emerged as a solution that provides a much needed flexibility and scalability in the era of multi-cores. This article presents an...
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| Main Author: | Harmanani, Haidar M. (author) |
|---|---|
| Other Authors: | Salamy, Hassan (author) |
| Format: | article |
| Published: |
2013
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| Online Access: | http://hdl.handle.net/10725/3526 http://dx.doi.org/10.1080/00207217.2012.713016 http://www.tandfonline.com/doi/abs/10.1080/00207217.2012.713016 |
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