Thermal-aware test scheduling using network-on-chip under multiple clock rates
The increasing trend in the number of cores on a single chip has led to scalability and bandwidth issues in bus-based communication. Network-on-chip (NoC) techniques have emerged as a solution that provides a much needed flexibility and scalability in the era of multi-cores. This article presents an...
محفوظ في:
| المؤلف الرئيسي: | Harmanani, Haidar M. (author) |
|---|---|
| مؤلفون آخرون: | Salamy, Hassan (author) |
| التنسيق: | article |
| منشور في: |
2013
|
| الوصول للمادة أونلاين: | http://hdl.handle.net/10725/3526 http://dx.doi.org/10.1080/00207217.2012.713016 http://www.tandfonline.com/doi/abs/10.1080/00207217.2012.713016 |
| الوسوم: |
إضافة وسم
لا توجد وسوم, كن أول من يضع وسما على هذه التسجيلة!
|
مواد مشابهة
-
An effective solution to thermal-aware test scheduling on network-on-chip using multiple clock rates
حسب: Harmanani, Haidar
منشور في: (2017) -
An optimal formulation for test scheduling network-on-chip using multiple clock rates
حسب: Harmanani, Haidar M.
منشور في: (2017) -
On Power-Constrained System-on-chip Test Scheduling Using Precedence Relationships
حسب: Harmanani, Haidar M.
منشور في: (2017) -
Power-constrained system-on-a-chip test scheduling using a genetic algorithm
حسب: Harmanani, Haidar M.
منشور في: (2006) -
AN ON CHIP ALL-DIGITAL CONFIGURABLE CLOCK GENERATOR FOR ASICS' AT-SPEED TESTING
حسب: unknown
منشور في: (2020)