An automated temporal partitioning and loop fission approach for FPGA based reconfigurable synthesis of DSP applications

An automated temporal partitioning and loop fission approach for FPGA based reconfigurable synthesis of DSP applications

We present an automated temporal partitioning and loop transformation approach for developing dynamically reconfigurable designs starting from behavior level specifications. An Integer Linear Programming (ILP) model is formulated to achieve near-optimal latency designs. We, also present a loop restr...

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Bibliographic Details
Main Author: Ouaiss, I. (author)
Other Authors: Kaul, M. (author), Vemuri, R. (author), Govindarajan, S. (author)
Format: conferenceObject
Published: 2017
Online Access:http://hdl.handle.net/10725/5811
http://dx.doi.org/10.1109/DAC.1999.782017
http://libraries.lau.edu.lb/research/laur/terms-of-use/articles.php
http://ieeexplore.ieee.org/abstract/document/782017/
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http://hdl.handle.net/10725/5811
http://dx.doi.org/10.1109/DAC.1999.782017
http://libraries.lau.edu.lb/research/laur/terms-of-use/articles.php
http://ieeexplore.ieee.org/abstract/document/782017/

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