A 28 nm CMOS 10 bit 100 MS/s Asynchronous SAR ADC with Low-Power Switching Procedure and Timing-Protection Scheme

A 28 nm CMOS 10 bit 100 MS/s Asynchronous SAR ADC with Low-Power Switching Procedure and Timing-Protection Scheme

<div><p>This paper presents a 10 bit 100 MS/s asynchronous successive approximation register (SAR) analog-to-digital converter (ADC) without calibration for industrial control system (ICS) applications. Several techniques are adopted in the proposed switching procedure to achieve better...

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Bibliographic Details
Main Author: Fang Tang (116243) (author)
Other Authors: Qiyun Ma (9149834) (author), Zhou Shu (7420991) (author), Yuanjin Zheng (3701836) (author), Amine Bermak (1895947) (author)
Published: 2021
Subjects:
Engineering
Electrical engineering
SAR
ADC
high linearity
low power
switching procedure
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