A 28 nm CMOS 10 bit 100 MS/s Asynchronous SAR ADC with Low-Power Switching Procedure and Timing-Protection Scheme
<div><p>This paper presents a 10 bit 100 MS/s asynchronous successive approximation register (SAR) analog-to-digital converter (ADC) without calibration for industrial control system (ICS) applications. Several techniques are adopted in the proposed switching procedure to achieve better...
Saved in:
| Main Author: | |
|---|---|
| Other Authors: | , , , |
| Published: |
2021
|
| Subjects: | |
| Tags: |
Add Tag
No Tags, Be the first to tag this record!
|
| _version_ | 1864513517842857984 |
|---|---|
| author | Fang Tang (116243) |
| author2 | Qiyun Ma (9149834) Zhou Shu (7420991) Yuanjin Zheng (3701836) Amine Bermak (1895947) |
| author2_role | author author author author |
| author_facet | Fang Tang (116243) Qiyun Ma (9149834) Zhou Shu (7420991) Yuanjin Zheng (3701836) Amine Bermak (1895947) |
| author_role | author |
| dc.creator.none.fl_str_mv | Fang Tang (116243) Qiyun Ma (9149834) Zhou Shu (7420991) Yuanjin Zheng (3701836) Amine Bermak (1895947) |
| dc.date.none.fl_str_mv | 2021-11-19T03:00:00Z |
| dc.identifier.none.fl_str_mv | 10.3390/electronics10222856 |
| dc.relation.none.fl_str_mv | https://figshare.com/articles/journal_contribution/A_28_nm_CMOS_10_bit_100_MS_s_Asynchronous_SAR_ADC_with_Low-Power_Switching_Procedure_and_Timing-Protection_Scheme/25709838 |
| dc.rights.none.fl_str_mv | CC BY 4.0 info:eu-repo/semantics/openAccess |
| dc.subject.none.fl_str_mv | Engineering Electrical engineering SAR ADC high linearity low power switching procedure |
| dc.title.none.fl_str_mv | A 28 nm CMOS 10 bit 100 MS/s Asynchronous SAR ADC with Low-Power Switching Procedure and Timing-Protection Scheme |
| dc.type.none.fl_str_mv | Text Journal contribution info:eu-repo/semantics/publishedVersion text contribution to journal |
| description | <div><p>This paper presents a 10 bit 100 MS/s asynchronous successive approximation register (SAR) analog-to-digital converter (ADC) without calibration for industrial control system (ICS) applications. Several techniques are adopted in the proposed switching procedure to achieve better linearity, power and area efficiency. A single-side-fixed technique is utilized to reduce the number of capacitors; a parallel split capacitor array in combination with a partially thermometer coded technique can minimize the switching energy, improve speed, and decrease differential non-linearity (DNL). In addition, a compact timing-protection scheme is proposed to ensure the stability of the asynchronous SAR ADC. The proposed ADC is fabricated in a 28 nm CMOS process with an active area of 0.026 mm2. At 100 MS/s, the ADC achieves a signal-to-noise-and-distortion ratio (SNDR) of 51.54 dB and a spurious free dynamic range (SFDR) of 55.12 dB with the Nyquist input. The measured DNL and integral non-linearity (INL) without calibration are +0.37/−0.44 and +0.48/−0.63 LSB, respectively. The power consumption is 1.1 mW with a supply voltage of 0.9 V, leading to a figure of merit (FoM) of 35.6 fJ/conversion-step.</p><p> </p></div><h2>Other Information</h2> <p> Published in: Electronics<br> License: <a href="https://creativecommons.org/licenses/by/4.0/" target="_blank">https://creativecommons.org/licenses/by/4.0/</a><br>See article on publisher's website: <a href="https://dx.doi.org/10.3390/electronics10222856" target="_blank">https://dx.doi.org/10.3390/electronics10222856</a></p> |
| eu_rights_str_mv | openAccess |
| id | Manara2_e7343cd6dbec9c6bcf64b4313ec09e13 |
| identifier_str_mv | 10.3390/electronics10222856 |
| network_acronym_str | Manara2 |
| network_name_str | Manara2 |
| oai_identifier_str | oai:figshare.com:article/25709838 |
| publishDate | 2021 |
| repository.mail.fl_str_mv | |
| repository.name.fl_str_mv | |
| repository_id_str | |
| rights_invalid_str_mv | CC BY 4.0 |
| spelling | A 28 nm CMOS 10 bit 100 MS/s Asynchronous SAR ADC with Low-Power Switching Procedure and Timing-Protection SchemeFang Tang (116243)Qiyun Ma (9149834)Zhou Shu (7420991)Yuanjin Zheng (3701836)Amine Bermak (1895947)EngineeringElectrical engineeringSARADChigh linearitylow powerswitching procedure<div><p>This paper presents a 10 bit 100 MS/s asynchronous successive approximation register (SAR) analog-to-digital converter (ADC) without calibration for industrial control system (ICS) applications. Several techniques are adopted in the proposed switching procedure to achieve better linearity, power and area efficiency. A single-side-fixed technique is utilized to reduce the number of capacitors; a parallel split capacitor array in combination with a partially thermometer coded technique can minimize the switching energy, improve speed, and decrease differential non-linearity (DNL). In addition, a compact timing-protection scheme is proposed to ensure the stability of the asynchronous SAR ADC. The proposed ADC is fabricated in a 28 nm CMOS process with an active area of 0.026 mm2. At 100 MS/s, the ADC achieves a signal-to-noise-and-distortion ratio (SNDR) of 51.54 dB and a spurious free dynamic range (SFDR) of 55.12 dB with the Nyquist input. The measured DNL and integral non-linearity (INL) without calibration are +0.37/−0.44 and +0.48/−0.63 LSB, respectively. The power consumption is 1.1 mW with a supply voltage of 0.9 V, leading to a figure of merit (FoM) of 35.6 fJ/conversion-step.</p><p> </p></div><h2>Other Information</h2> <p> Published in: Electronics<br> License: <a href="https://creativecommons.org/licenses/by/4.0/" target="_blank">https://creativecommons.org/licenses/by/4.0/</a><br>See article on publisher's website: <a href="https://dx.doi.org/10.3390/electronics10222856" target="_blank">https://dx.doi.org/10.3390/electronics10222856</a></p>2021-11-19T03:00:00ZTextJournal contributioninfo:eu-repo/semantics/publishedVersiontextcontribution to journal10.3390/electronics10222856https://figshare.com/articles/journal_contribution/A_28_nm_CMOS_10_bit_100_MS_s_Asynchronous_SAR_ADC_with_Low-Power_Switching_Procedure_and_Timing-Protection_Scheme/25709838CC BY 4.0info:eu-repo/semantics/openAccessoai:figshare.com:article/257098382021-11-19T03:00:00Z |
| spellingShingle | A 28 nm CMOS 10 bit 100 MS/s Asynchronous SAR ADC with Low-Power Switching Procedure and Timing-Protection Scheme Fang Tang (116243) Engineering Electrical engineering SAR ADC high linearity low power switching procedure |
| status_str | publishedVersion |
| title | A 28 nm CMOS 10 bit 100 MS/s Asynchronous SAR ADC with Low-Power Switching Procedure and Timing-Protection Scheme |
| title_full | A 28 nm CMOS 10 bit 100 MS/s Asynchronous SAR ADC with Low-Power Switching Procedure and Timing-Protection Scheme |
| title_fullStr | A 28 nm CMOS 10 bit 100 MS/s Asynchronous SAR ADC with Low-Power Switching Procedure and Timing-Protection Scheme |
| title_full_unstemmed | A 28 nm CMOS 10 bit 100 MS/s Asynchronous SAR ADC with Low-Power Switching Procedure and Timing-Protection Scheme |
| title_short | A 28 nm CMOS 10 bit 100 MS/s Asynchronous SAR ADC with Low-Power Switching Procedure and Timing-Protection Scheme |
| title_sort | A 28 nm CMOS 10 bit 100 MS/s Asynchronous SAR ADC with Low-Power Switching Procedure and Timing-Protection Scheme |
| topic | Engineering Electrical engineering SAR ADC high linearity low power switching procedure |