FPGA-based Parallel Hardware Architecture for Real-time Object Classification
A Master of Science thesis in Computer Engineering by Murad Mohammad Qasaimeh entitled, "FPGA-based Parallel Hardware Architecture for Real-time Object Classification," submitted in June 2014. Thesis advisor is Dr. Tamer Shanableh and co-advisor is Dr. Assim Sagahyroon. Available are both...
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| Format: | doctoralThesis |
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2014
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| Online Access: | http://hdl.handle.net/11073/7511 |
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