APA (7th ed.) Citation

Ouaiss, I., Kaul, M., Vemuri, R., & Govindarajan, S. (2017). An automated temporal partitioning and loop fission approach for FPGA based reconfigurable synthesis of DSP applications.

Chicago Style (17th ed.) Citation

Ouaiss, I., M. Kaul, R. Vemuri, and S. Govindarajan. An Automated Temporal Partitioning and Loop Fission Approach for FPGA Based Reconfigurable Synthesis of DSP Applications. 2017.

MLA (9th ed.) Citation

Ouaiss, I., et al. An Automated Temporal Partitioning and Loop Fission Approach for FPGA Based Reconfigurable Synthesis of DSP Applications. 2017.